1 Introduction
The 3G system can provide multiple types of high-quality multimedia services, achieve global seamless coverage, and have global roaming capabilities compatible with fixed networks.
COS (Chip Operation System) is a smart card chip operating system. It is an important supporting platform for the intelligent card to implement the "smart" operating system software. The excellent smart card COS system will enable smart cards to achieve "safe and reliable application intelligence." At present, 3GCOS mainly has three problems: the architecture model, the selection of key technologies and the establishment of coverage models. The selection of the architecture model and key technologies mainly reflects the efficiency and scalability of the COS system. The establishment of the coverage model is mainly to meet the needs of different hardware UICCs. In order to solve the problem of system efficiency and expansion, this paper adopts a semi-hierarchical structure model that combines the advantages of hierarchical structure and micro-kernel structure; in order to solve the adaptability problem of COS system on different hardware without increasing the code of COS system Quantity, the system decides to adopt the method of mapping from the overlay model to the special model. When the mask can be loaded into the specific UICC hardware, the overlay model abstracts the special model according to the UICC hardware features of the specific mask, instead of directly covering the model. The mask is transferred to the UICC, which can reduce the amount of code of the COS system and relatively increase the amount of user data that can be stored.
2 Architecture design
At present, there are four main types of system models: the monolithic structure model, the hierarchical structure model, the customer/service model, and the REO model. Through detailed analysis of the advantages and disadvantages of each of the four models and the applicable scenarios, this paper is based on 3GCOS. The design goals and design principles of the system propose a semi-hierarchical structure model suitable for the actual development of the system, as shown in Figure 1.
2.1 Functional division of each module
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The COS structural model can be divided into two levels as a whole: the functional module layer and the micro-kernel layer. Among them, the functional layer mainly implements the application logic processing function of COS, and mainly includes a communication management module, a security management module, a command interpretation module, and a file management module.
(1) Functional module layer
Communication management module: Performs parity check, accumulation and packet length check on the data received in the I/O input buffer to determine the correctness of the means, and does not judge the content of the information. For the standard of judgment, refer to ISO 7816-4 APDU. Instruction structure; receives information after security management, command processing, file management processing, and packages into a complete data frame according to the ISO 7816 APDU instruction structure requirements, and sends it to the I/O output buffer.
The security management module: accepts the scheduling of the communication management module, and returns the processed data information to the communication management module; performs security verification by the communication management module; does not perform verification of the data content; when the security verification fails, directly The communication management module returns data.
The command interpretation module: accepts the scheduling of the security management module, and returns the processed data information to the security management module, that is, returns a response code corresponding to the command; needs to be authenticated on the data content; when the data content is not authenticated, directly Return data to the communication module.
File management module: accepts the scheduling of the command management module, and executes commands to return data to the command interpretation module.
(2) Microkernel layer
Micro-core overall function: Provide hardware support for the logic processing of the functional layer to realize communication between the card and the terminal. The microkernel is divided into three parts: the conversion layer, the hardware interface layer, and the hardware. The transformation layer accepts the scheduling of the functional layer, and converts the scheduling of the functional layer into a call to the underlying driver interface, and provides a unified upward interface to the functional layer to implement management of various underlying hardware drivers of the overlay model, when converted from the overlay model to In the special model, the specific hardware configuration of the underlying driver is implemented, and the redundant underlying driver in the overlay model is stripped. In the special model, the functional layer implements a transparent call to the underlying driver; the hardware interface layer mainly implements the driving scheduling of the underlying hardware.
2.2 State transition and scheduling relationship between functional modules
The relationship between the modules of the function layer is represented by the program scheduling request and the data response relationship. The output of the module is the program scheduling request, the input is the data response obtained after the scheduling, the scheduling and the corresponding are represented by the transaction, and the transaction represents a set of data. And a set of operations on the data. The state transition and scheduling relationship between modules in the 3GCOS functional layer is shown in Figure 2.
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Figure 2 Module state transition and scheduling diagram
Among them, the transaction 2 and the transaction 3 in the above figure represent a communication relationship between the card and the terminal.
3 key technologies
3.1 Design of the main scheduling process of the system
3.1.1 Main scheduling process
The scheduling process of the COS system is divided into the main scheduling process and the functional sub-process. The main process can use the polling mode or the interrupt mode to receive the terminal input command. Because of the large system overhead of the polling mode, the interrupt scheduling mode is adopted in the 3GCOS system. The execution steps of the 3GCOS main scheduling process are as follows:
(1) The card is powered on and reset;
(2) transmitting the first byte of the ATR reset response command;
(3) Initialize the system operating environment: Initialize the security environment, clear the I/O input and output buffer APDU—IN—buffer, AP. DU—OUT— buffer;
(4) sending the remaining bytes of the ATR;
(5) waiting for an interrupt command signal;
(6) scheduling an interrupt handler to obtain an interrupt service program entry address corresponding to the interrupt source;
(7) scheduling execution of the interrupt service routine according to the interrupt service program entry address;
(8) judging the integrity of the input buffer APDU command;
(9) If the APDU instruction is incomplete, return 5 and continue to wait for the interrupt command signal;
(10) If the APDU command is complete, the system closes the interrupt, and the scheduling function executes the sub-process to process the command, and returns the processing result to the output buffer APDU—OUT—buffer:
(11) calling the output I/O output driver, and sending the APDU response command to the terminal;
(12) Clear the input and output, buffer;
(13) Open the interrupt and return.
The main sequence execution flow chart is shown in Figure 3.
3.1.2 Algorithm Description
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The program has completed the overall software testing, the system is stable and reliable, in line with ISO/IEC 7816 and ISO/IECI443 TYPE B standards and "China Financial Integrated Circuit (IC) Card Specifications", "China Financial Integrated Circuit (IC) Card Application Standards such as the Code are now undergoing user testing.
(Wen/Zhongyi Institute of Agricultural Technology Modern Education Technology Center, Guangdong University of Technology, School of Computer Science, Yi Yi, Chen Rongzheng, Huang Jian)
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