Talking about the Application of FPGA and USB Technology in Textile Digital Printing Machine

The industrial textile digital printing press system is divided into two parts: a printing press and a host PC. The textile printing press is not a stand-alone system. It is the command and image data received from the host PC. The printing operation is completed according to the instructions and image data. It will feedback its own working status to the device of the host PC. The interface part is the bridge that realizes the communication between the front controller in the printing press and the host PC.

Textile digital inkjet printers in real-time industrial sites require high transmission speeds. Communication between traditional digital inkjet printers and the host computer is mainly achieved through serial interfaces, parallel interfaces or interface cards provided by the mainboard of the host computer. Because of its low transmission speed, it has been unable to meet the needs of high-speed industrial production processes. USB technology solves the above problem well. Although the recently released USB3.0 protocol can theoretically reach the limit of 5 Gb/s transmission speed, the microprocessor currently integrated with USB3.0 is still in the experimental test phase. Postmarketing after comprehensive optimization. Therefore, the micro-processing chip supporting the USB2.0 protocol is still the main communication microprocessor selected in industrial high-speed printing and dyeing equipment.

FPGA is a field programmable gate array electronic integrated device. Because of its high integration, several large printed circuit boards realized with small and medium-sized integrated circuits are reduced to one or two VLSI circuits, which not only makes the control system much larger. Reduced, and the reliability of the system has been greatly improved. FPGA programmability can also make the textile digital press control system design, debugging, production and maintenance more flexible and convenient. With the rapid development of large-scale programmable logic devices FPGA, FPGA devices can play a superior performance and a greater role in such a motion control system. As an auxiliary circuit of textile digital printing press control system, it can replace many traditional logic circuits, simplifies system design, and can improve the reliability of the system, reduce the size of the circuit board, miniaturize the product, and also help protect intellectual property rights [1]. How to optimize the transmission performance of USB2.0 devices, break through the bottleneck of speed, and maximize the transmission speed is an urgent problem to be solved in the design of printers. This paper designs a USB 2.0-based high-speed industrial textile digital inkjet printer data transmission system, and then studies FPGA design optimization in the printing press system and realizes the overall improvement of USB 2.0 interface data transmission speed.

1 system design

For the characteristics of the textile printing press system, the system can be controlled and run by a PC, using the IJA mode inkjet printer nozzle, 510 holes per nozzle, 180 dpi. In order to increase the printing speed, grouping nozzles are used, each group is 6 colors or 8 colors, a total of 3-6 groups are optional. Supports printing 1~4 grayscale images. The main controller of the system consists of a data transmission board and a motion control board. It is mainly composed of an S3C2440 processor ARM core board, a 400 MHz working frequency, 64 MB of SDRAM, 16 MB of Flash, support for LCD interface, and support for IIC. Interface, support 16 bit external bus addressing, support DMA. The main controller receives the control commands and image data from the PC, detects and controls the various movements in the system, synchronizes the movement with the jets, and transfers the image data required by the jets to the head plate.

When the main controller works online, it must be able to communicate with the PC in two directions, receive image data and various configuration information and control commands from the PC, and at the same time transmit the status of the system to the PC. Consider using the USB2.0 interface protocol. Because S3C2440 does not support USB2.0 protocol, the system expands the USB expansion interface chip of CY7C68013A, in order to buffer this chip and ARM bus, the system has expanded a piece of FPGA. The FPGA is responsible for USB interface buffering, motion control, position, speed detection, level detection of secondary cartridges, control of secondary cartridge pump, image data format conversion and transmission of the nozzle plate, control of ignition nozzles by nozzle position and color sequence. .

This article mainly discusses the data communication between the PC host and the main control board of the printing press. In view of the demand of the system, this communication module adopts EZ-USB FX2LP one-chip computer CY7C68013A that supports USB2.0 high-speed data transmission as the interface chip. FPGA EP1C6Q-240 is used as the external logic of the USB interface chip to complete the communication between the FPGA and the USB interface chip. When the host computer sends a control signal, after the interface chip CY7C68013A resolves and communicates with the FPGA. When the system main controller detects the start data transmission and data format command issued by the host computer, the data transmission is started. The data packet parsed by the SIE is synchronized to the internal slave FIFO mode through the CY7C68013A via the USB interface chip CY7C68013A. The FIFO buffer is quickly stored in the FPGA's internal FIFO, and then the main controller ARM controls the FPGA to transfer data from the host through the USB head to read data from the head controller and then to the 6-color head.

2 Hardware Design

2.1 USB interface section

The printing of textile digital presses is done in units of lines, and printing must be done at a constant rate during each line of printing. At the end of each row, the nozzle cart should be accelerated and decelerated and reversed, and the cloth roller should be rolled into the cloth for the next line of printing. Constant speed prints must be guaranteed with a constant image data rate. The higher the printing speed requirement, the higher the requirement for the transmission speed of image data. In this communication system, the CY7C68013A chip is selected. The architecture adopted is EZ-USB FX2LP. It is a USB2.0 chip that has been improved on the basis of FX2. It integrates the enhanced 8051 core and uses low power. Power consumption design represents the leading level in the industry. It is a new generation of USB2.0 high-speed controller compliant architecture and is fully compatible with FX2[2].

In the PC and FX2LP front-end control system, FX2LP's built-in CPU is responsible for receiving commands from the host PC to control the movement of the printing press, and synchronize the image data. The image data is sent to the print head through the FPGA and ARM, and at the right time Command the nozzle to do an ignition action. If traditional methods are used, the FX2LP's built-in CPU directly addresses and stores the image memory of the image data sent from the host computer, and sends the image data and the motion control to the FPGA synchronously. Then the FPGA controls the firing of the nozzle with the ARM. These actions require Complex instruction sequences, multiple memory accesses, require a lot of time, and it is almost impossible to achieve high data transfer rates.

Analysis of the working mechanism of the textile ink jet printer found that the front-end control system does not need to understand the image data transmitted from the host computer, all it has to do is synchronize the image data, and transmit the image data to the print head at an appropriate timing. Therefore, the image data can be accessed without going through the built-in CPU of the FX2LP, and can be sent to the printhead directly under the synchronization of the CPU. Since EZ-USB FX2 provides a unique architecture, the EZ-USB CPU can be located on the data path of the USB host and external logic. In order to achieve the maximum data bandwidth, EZ-USB directly connects the USB host with external logic, thereby bypassing the CPU, allowing the USB interface and the external application environment to directly share the FIFO, while the microprocessor can not participate in data transmission [4]. No need to implement the 8051 firmware program inside the USB interface chip to directly realize the data exchange between the endpoint FIFO and the external. This kind of processing framework called “quantum FIFO” can well solve the bandwidth bottleneck caused by the ordinary microprocessor's forwarding mode. [3].

Through the above analysis, the system adopts a method of bypassing image data. Use the 4K endpoint FIFO shared internally by the CY7C68013A as temporary storage for the image. The input endpoint of the FIFO memory directly receives the image pixel data of the USB host. The output endpoint data of the FIFO memory is read synchronously by the FPGA. The read data is sent to the print head via the ARM control instructions and the hardware channel. Therefore, the transmission speed of the image data is no longer closely related to the memory address cycle of the CPU of the EZ-USB, so that high-speed data transmission between the PC and the head can be realized by using this bypass fast path. The role of the FIFO also appears to be to create a buffer between high-speed USB transfers and medium-speed continuous print requests.

2.2 FPGA bridge section

Because CY7C68013A chip is selected as the USB2.0 interface chip, and the interface frequency of this chip is different from the bus timing of the main controller of the system, the chip cannot be directly connected to the main controller bus. Therefore, FPGA is considered as a bridge, and thus it is needed. The chip interfaces with the internal bus of the FPGA, taking into account the difference in the data transfer rate, and at the same time establishing a USB data buffer within the FPGA. The buffer consists of FIFOs and completes the exchange of information with the host controller. At the same time, FPGA as an external control logic of the Slave FIFO mode provides USB chip select, write data clock, and endpoint selection signals to implement data read and write control.

(1) Interface with USB chip

The FPGA internal bus is a synchronous 32 bit bus. The bus signals include 11 address line addr, 32 bit data input data_i, 32 bit data output data_o, write control input we, bus cycle signal cyc, latch signal stb, and response signal output ack. And the system clock signal clk and system reset signal rst, byte select signal sel.

(2) FIFO selection and establishment

Since both ends of the FIFO are to operate at different rates, the FIFOs used operate with different clocks, write to the USB_IFCLK as the synchronization clock, and read out the system clock clk_i as the synchronization clock. The write request line SLRD is synchronized with the write clock. When the FIFO is not full and the USB chip is not empty, a write request is always generated. This ensures that the FIFO automatically reads data from the USB chip, reducing the burden of software judgment.

Since the FIFO modules using different clocks cannot automatically generate near full and near empty signals, a half full signal is used, which is obtained by reading the highest bit of the word rdusedw. In this way, as long as the FIFO capacity is properly selected, the ARM can determine the half-full signal. Once there is a half-full signal, the ARM can no longer judge, read and read half of the data in the FIFO. Considering that the nozzle requires at least 1 KB of data for each shot, the FIFO is chosen to have a capacity of at least 16 bits and 2 KB. When the ARM detects that the FIFO is not half full, if the FIFO is not empty, data can still be read. However, for each read of a word, it must be checked whether the FIFO is empty, and the read rate cannot be high.

3 Software Design

3.1 USB Firmware

USB firmware is a program running on a microcontroller integrated in CY7C68013A. Cypress's EZ-USB FX2 development kit provides users with a firmware library (Ezusb.lib) and a firmware framework, both of which are based on KEIL. Developed by C51. When using the firmware framework for specific firmware development, the firmware framework has implemented functions such as initialization, re-enumeration, and power management. For the user, it is only necessary to add code at the reserved position of the firmware architecture to complete the specific function [4].

In the system's firmware programming, the initial setup function TD_Init() and the descriptor table file Dscr.a51 are used to complete system initialization and endpoint configuration. In order to optimize the data transmission speed, the dual-end combination mode is configured to realize high-speed batch transmission, and the initial value of the relevant special function register is set to realize the automatic transmission function of the synchronous Slave FIFO of the system [5].

The firmware program starts a USB transfer when it receives a print request command from the host computer. When the ARM initiates the control signal to start the carriage movement to the printing position, ARM reads the image data from the FPGA internal FIFO and starts the head firing signal to complete the printing of one pixel. Then continue the car movement and start the next printing. When the printing is finished once, ARM returns the system status to the PC via CY7C68013A, and CY7C68013A ends the data transmission. The ARM master program commands the cart to slow down, stop, and initiate the roll motion. After the rollout is completed, an action flow ends, waiting to receive the next command.

3.2 Drivers

The USB device driver is responsible for establishing the connection between the host and the device. The EZ-USB FX2LP development kit provided by Cypress Inc. contains the CyUSB.sys file. This is a generic device driver that supports USB 2.0 in compliance with the WDM specification. Only a few modifications to the VID, PID, etc. are required to develop the application. Meet the application needs of the system.

By customizing the driver's CyUSB.inf file and then using the Windows Device Manager, any USB device can match the CyUSB.sys driver. An important feature of the driver for general-purpose use is that it can be custom designed without recompilation. By modifying the driver's .inf file, it can make it notify a unique globally unique identifier (GUID). This will allow different copies of the driver to coexist on a PC moderately. In addition, the .inf file also allows the driver to perform a series of pre-recorded control endpoint transfers. This allows customized design of the driver's startup characteristics based on the Vendor ID and Product ID of the device to which it is connected [6].

3.3 Application

Hosts and devices generally communicate data through the master-slave mode. The host application sends command packets to the device. After the device receives the command data, it receives data from the host. The host application program completes the control and communication of the device through the device driver, and is written in VC++6.0.

In order to improve the transmission speed and efficiency, and also to prevent application programs from reading and writing data when the "fake crash" phenomenon, the application uses a multi-threaded method to write, generally put the data transmission in another thread, that is, open a batch The transfer thread is a secondary thread that is different from the main thread. The bulk transfer thread is responsible for writing data to the device and communicating with the main thread via a message transfer mechanism. The main thread is responsible for interface management, data processing, sending command packets to the device, and starting/stopping bulk transfer threads.

In the thread loop, mainly call BeginDataXfer (), WaitForXfer (), FinishDataXfer () 3 functions. Where BeginDataXfer() initiates an asynchronous transfer and returns immediately. That is, after initiating this transfer of bytes, it will not wait for the transfer to complete, but will immediately start the next byte data transfer; WaitForXfer() is the maximum waiting time for asynchronous transfer; only when TransferDataXfer() is executed will the transfer be started. Data is written to the device memory. In addition, if you want to transfer data that is not an integer multiple of 512 B, and it is not a complete transfer, you should use the SetXferSize() function to reset the transfer size in the bulk transfer thread, otherwise the data will not be synchronized.

The system has been tested to achieve the desired inkjet effects and speed requirements. Through the use of FPGA devices, the number of discrete components is reduced, the system design is simplified, the system's programmable performance is enhanced, the system is easy to maintain and upgrade, and it is conducive to technical confidentiality and intellectual property protection. The design scheme has been applied to the actual development of the project.